What the meaning of "|" and "&" in the if statement of Verilog [duplicate]
I saw the following Verilog if statement code. Wanted to know what's the meaning/purpose of "|" and "&" before the the dl and dl_n? Anyone kind to explain? Or what's the keyword I should look for from google for this?
if((count_w > 1) && ~(|dl==1'b0 && &dl_n==1'b1)) begin //Statements end 3 Answers
These are called reduction operators in Verilog.
| is used as an OR, and the & used as an AND.
Following are the reduction operators:
| Operator| Type | |_________|_________| | & | And | | ~& | Nand | | | | Or | | ~| | Nor | | ^ | Xor | | ~^ | Xnor | |_________|_________| These are the unary reduction operators. |val is reduction OR, and &val is reduction AND.
Reduction operators:
- & (AND)
- ~& (NAND)
- | (OR)
- ~| (NOR)
- ^ (XOR)
- ~^ or ^~ (XNOR)
Nevertheless, don't confuse with "&&" as this is a local AND. Also, the reduction should be right next to the variable, if positioned between two variables like "a & b" , it is a bit-wise operation, an example:
wire c = &a ^ |b; /* The value of a has an AND reduction, b an OR reduction, and the results of those reductions takes a bit wise XOR operation between them, this assigned to c.*/ 
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